C++ Software Engineer – RTL Design and Synthesis

Job title:

C++ Software Engineer – RTL Design and Synthesis

Company:

Siemens

Job description

Job Description:Siemens Digital Industries Software – Transform the everyday.Let’s make the difference together!Siemens Digital Industries (DI) is an innovation leader in automation and digitalization. Closely, collaborating with partners and customers, we care about the digital transformation in the process and discrete industries. With our Digital Enterprise portfolio, we provide and encourage companies of all sizes with an end-to-end set of products, solutions and services to integrate and digitalize the entire value chain. Meaningful optimization for the specific needs of each industry, our outstanding portfolio supports customers to achieve greater efficiency and flexibility. We are constantly adding innovations to its portfolio to integrate groundbreaking future technologies. We have our global headquarters in Nuremberg, Germany, and have around 75,000 employees internationally.We offer a role with responsibility, independence and the possibility to contribute proactive. We foster a teamwork culture with room for individual developmentPlease visitAbout the role / SegmentSiemens EDA, is looking for a C++ Software Engineer – RTL Design and Synthesis who is required to understand, design and implement algorithm-centric solutions in the high-level synthesis. The role is for industry leading high level synthesis tool – Catapult-C which takes ANSI C/C++ and SystemC inputs and generates register transfer level (RTL) code targeted to FPGAs and ASICs.Catapult–C tool is used by top hardware design companies for designing cutting edge semiconductor chip design in automotive/machine learning/wireless design/video and image processing etc.The offered position includes:

  • Working on the physical design execution from C to GDS and the power estimation/optimization
  • Conducting complex analyses and debug of results using statistics and data predictions to identify issues or areas for improvement.
  • Work with customers, research partners and academia to drive future innovation-related initiatives including the development of new scripts and flows.
  • Leverage infrastructure and learning developed from such initiatives to products in Siemens EDA
  • Analyze and improve PPA for HLS-generated RTL by improving Flows and Methodologies.
  • Participate in the specification, architecture, design, and development of features.
  • Be a force for improving development processes and product quality.
  • Work effectively with globally distributed engineering teams.

These are exciting times in our space – we are growing fast and working on ambitious new initiatives.Area of responsibilityYou will be responsible for:

  • Evaluating Catapult as a C2GDS tool, analyzing internal/customer designs and improve QofR OOTB
  • Defining new algorithms to improve correlation between HLS and physical netlist
  • Contributing to the implementation of those algorithms.

Your qualificationsTechnical Skills (Must have):

  • Strong programming knowledge in C/C++ and object-oriented design skills.
  • Excellent algorithm and data-structure design skills with theoretical and practical experience in implementation of complex algorithms.
  • Script-programming skills with languages such as TCL, Perl, Python, Shell, etc.
  • Familiarity with Unix/Linux operating systems.
  • Strong analytical and problem-solving capabilities.

Technical Skills (Strongly desirable to cover few of those skills):

  • RTL Synthesys
  • STA
  • Floorplanning
  • Placement
  • Physical implementation
  • CTS

Technical Skills (Desirable) : In few of the below areas

  • Understanding/Prior experience in design / implementation of EDA algorithms in the areas of logic synthesis and optimization / High level synthesis / Timing analysis / Formal verification
  • Experience in hardware modelling in VHDL/Verilog/SystemC
  • Understanding of digital design for ASIC or FPGA.
  • Hardware architecture and trade offs for digital arithmetic design.
  • System level hardware modelling in areas of Virtual prototyping / Hardware-software co-design etc.
  • Prior experience in working/designing of complex algorithms and optimization
  • Experience in Compiler design – Language parsing/ Abstract syntax tree optimization/transformation / Loop optimizations / Parallel compiler /Software pipelining / Register allocation etc

General Skills: Strong positive attitude, Good presentation and communication skills, Self-driven and self-motivating, Able to implement technical solutions independently, Relationship building capabilities, Team player.Required Education, and Experience

  • Bachelors with 4+ years or Master’s degree with 2+ years or PhD graduates ( fresh or experienced) in EDA or related areas with degree in Computer Science or equivalent.

The Ideal Candidate should demonstrate:

  • Previous experience with product development or academic research.
  • Strong analytical and problem-solving capabilities.
  • Ability to collaborate as part of globally distributed team
  • Fluency in English

Working at Siemens SoftwareWhy us?Working at Siemens Software means flexibility – Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you’d expect from a world leader in industrial software.We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.Siemens Industry Software is an equal opportunities employer and does not discriminate unlawfully on the grounds of age, disability, gender assignment, marriage, and civil partnership, pregnancy and maternity, race, religion or belief, sex, sexual orientation, or trade union membership.Siemens. Making real what mattersIf you want to make a difference – make it with us!#LI-EDA#LI-DS1#LI-Hybrid

Expected salary

Location

Meylan, Isère

Job date

Sat, 09 Mar 2024 06:17:48 GMT

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