Lead MTS RTL Logic Design

Location:

(Vught) Netherlands

Salary:

80K plus – negotiable

Type:

Permanent

Main Industry:

Search Engineering Jobs

Advertiser:

microTECH Global Ltd

Job ID:

131997087

Posted On:

13 June 2025

Job Title: Lead MTS

Position: Permanent, On-site – Hybrid

Location: The Netherlands, Vught

Salary Range: 80K – 90K EUR per annum

Client Information:

Seeking to hire an exceptional Lead Member of Technical Staff Logic Design Engineer.

You’ll be joining the Silicon IP team.

You must have experience of working with complex IP design and have architecture background.

Responsibilities:

Design and implementation of complex secure silicon IP’s

-Planning: lead other digital designers, manage projects, estimate cost (effort)
-Architecture: Design block specification, documentation, have/encourage innovative ideas/patents for current and future products
-Implementation: RTL design in Verilog or System Verilog /Experience with high-performance RTL design (pipeline/parallel processing) /Experience with low-latency /area RTL design
-Verification: work with verification team on planning and execution, simulation, debugging simulations
-Flow and methodology: work in a dynamic and interdisciplinary R&D group that influences and guides Rambus’ technical direction by understanding and contributing to flow and methodology development
-Interact with technical leaders of the company and senior staff in engineering, product management, sales and FAE’s to help ensure successful development of high value products

Requirements:

-BS or MS degree in Hardware Engineering, Computing Science or comparable level
-Strong experience in the security or chip industry in relevant engineering positions at R&D centres or system laboratories
-In depth knowledge of SoC, Silicon IP and/or FPGA logic design flows
-In depth knowledge of hardware description languages (Verilog, VHDL, SystemVerilog) and scripting languages
-In depth knowledge of cryptography, security protocols and security implementations
-Good knowledge of verification flows (assertion-based design strategies, code coverage, functional coverage, test plans etc.)
-Strong written and verbal communication skills: Ability to explain complex concepts in front of technical audience
-Good documentation skills, both in text and drawings

Beneficial Experience

-Familiarity with IP integration, IP core delivery, and handoff issues
-Ability to work with technical writers in the production of technical documentation

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