PhD thesis: Graph Neural Networks for Predicting Power Consumption in Digital Electronic Architectures

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Entité de rattachement

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Référence

2024-31285  

Description de la Direction

The French Atomic Energy and Alternative Energies Commission (CEA) is a major player in research, development and innovation. This technological research organization is active in three main areas: energy, information and health technologies, and defense. Recognized as an expert in its fields, CEA is fully integrated into the European research area and is expanding its presence internationally. The LIST institute, located in Saclay, has the mission of contributing to technology transfer and promoting innovation in the field of parallel computing systems.

Description de l’unité

The Environmental Design and Architecture Laboratory (LECA), within the Digital Systems and Integrated Circuits Department (DSCIN), is a multidisciplinary technological research team comprising experts in hardware IP design and simulation tools. The developed simulation tools rely on various models with different levels of abstraction, tailored to meet the requirements of hardware/software co-design and co-validation.

Description du poste

Domaine

Mathématiques, information  scientifique, logiciel

Contrat

CDD

Intitulé de l’offre

PhD thesis: Graph Neural Networks for Predicting Power Consumption in Digital Electronic Architectures

Statut du poste

Non Cadre

Durée du contrat (en mois)

36

Description de l’offre

Power consumption analysis is an important step in the development of a digital architecture. This power analysis is necessary early on in the RTL (Register Transfer Level) coding stage when the most advantageous modifications can be made. As designs become larger, power analysis relies on longer simulation traces and becomes nearly impossible because the process generates huge simulation files, resulting in long power analysis execution times. To address this issue, power models can be used to accelerate this analysis stage. There is a wide range of research on power modeling at the RTL level, mainly based on analytical or learning approaches. Analytical power modeling attempts to correlate application profiles such as memory behavior, branch behavior, etc., with microarchitecture parameters to create a power model. Meanwhile, learning-based power modeling generates a model based on the simulation trace of the design and a reference power close to actual consumption. Learning-based power modeling is gaining popularity as it is easier to implement than the analytical approach and does not require extensive design knowledge. These ML-based methods have shown impressive improvements over analytical methods. However, classical ML methods (linear regression, neural networks, etc.) are more suitable for generating a model for a specific architecture, making them difficult to use for generating a generalizable model. Thus, in the past two years, some studies have begun using graph neural networks (GNNs) to address model generalization in the field of electronic design automation (EDA). The advantage of a GNN over classical ML approaches is its ability to learn directly from graphs, making it more suitable for EDA problems.
The objective of this thesis is to design a generalizable power consumption model for a digital electronic architecture based on GNN. The developed generalizable model should be capable of estimating, in addition to average consumption, the cycle-by-cycle consumption of any digital electronic architecture. Very few works exist in the state of the art on the use of GNNs for consumption estimation, and the models designed in these works are only capable of estimating the average consumption of an architecture. Moreover, several important research questions are not addressed in these works, such as:

• the number of data (architectures) needed for model generalization,
• the impact of graph structure during learning,
• the selection of architectures used for learning and testing,
• the choice of features, etc.

Thus, during this thesis, these questions will be studied to understand their impact during model generation.
The data generated by the GNN, or Graph Embeddings, are then fed into another model. This model can be a conventional neural network, a transformer, or a Large Language Model (LLM). During this thesis, identifying the optimal model to facilitate generalization will also be an area of exploration.

Profil du candidat

• Master’s degree in computer science/electronics.
• Good experience/knowledge in machine learning.
• Experience/knowledge in digital electronics design is also a plus.
• Excellent Python programming skills. Proficiency in VHDL and/or Verilog programming would be a plus.
• Strong analytical and experimental skills will be highly appreciated.

In accordance with the commitments made by the CEA in favor of the integration of people with disabilities, this job is open to everyone.

Localisation du poste

Site

Saclay

Localisation du poste

France, Ile-de-France, Essonne (91)

Ville

  Saclay

Critères candidat

Langues

Anglais (Courant)

Formation recommandée

Master 2

Demandeur

Disponibilité du poste

01/10/2024