We have an exciting opportunity available for a Senior Functional Verification Engineer based in Spain.
Role Overview:
We are seeking a Senior Functional Verification Engineer to work closely with architecture, design, physical implementation, and software teams to ensure our systems meet the highest quality standards. The role involves high-level modeling, UVM-based verification, HW/SW co-debug, and simulation acceleration support.
Key Responsibilities:
• Analyse system and architecture requirement documents to define and guide verification strategies.
• Develop and maintain verification environments using SystemVerilog, UVM, SystemC, and C++ (Stimulus, Checkers, Assertions, Trackers, Coverage).
• Execute verification plans, including design bring-up, regressions, and test debugging.
• Debug and root-cause issues using simulators, coverage tools, and close collaboration with design teams.
• Conduct coverage analysis, bug tracking, and regression testing to ensure verification completeness.
• Contribute to methodology enhancements and mentor junior engineers to strengthen team capability.
Qualifications:
• Master’s degree in Electrical/Computer Engineering or a related field.
• 7+ years of experience in verification of complex SoCs or IPs.
• Expertise in SystemVerilog/UVM, SystemC/C++, constrained-random verification, functional coverage, and design debug.
• Familiarity with formal verification (FPV, UPF) and HW/SW co-verification.
• Strong scripting skills in Bash, Perl, and Python.
• Excellent debugging, problem-solving, and communication skills.
• Professional proficiency in English.
Preferred / Plus:
• Experience with firmware-based verification.
• Exposure to metrics-driven verification environments.
• Knowledge of NoCs, PCIe, DDR, HBM, or other standard IPs and peripherals.
If you’re interested in exploring this opportunity, please get in touch with me and share your CV #
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