Senior IP Qualification Engineer

Arm teams develop groundbreaking SoC (system on Chip) which embeds the latest Arm Compute Sub-System IP (Intellectual Property) and other various IP coming from external IP companies.

We are looking for a creative and dedicated senior engineer to join the IP Qualification team and help verify these Third-Party IPs before they are embedded in SoC.

Such TPIP are standard-cells, I/O (general purpose and PHYs), SRAM/ROM memories, PLL, sensors, as well as sub-system Interfaces like LPDDR, USB, Ethernet or PCIe. You will join a best-in-class team in Sophia-Antipolis (French Riviera) as well as collaborate with multiple other groups inside of Arm.

Responsibilities:

You will ensure that the RTL design and related EDA models of the TPIP are in line with EDA tools used in Arm SoC design flow. You will verify that the methodology used for IP design and modeling aligns with the Arm SoC flow requirement. For that, you will use, improve, or develop Tcl scripts and then run them with the EDA tools from major providers for SoC flow steps. Such flow steps are functional and low-power verifications, synthesis, automatic Place&Route, Static Timing Analysis.

You will also make sure that the Interface-IP sub-systems (delivered as soft-IP or hardened) behave accurately and the receivables ares all consistent. You will analyze the deviations and share them with the SoC design teams for review and eventually report them to the IP providers for update. You will be also part of the continuous improvement discussions.

Required Skills and Experience :

• Five years of post-master degree work experience in RTL, lower-power and gate-level functional verification with System Verilog, static low-power verification (UPF-1801) at IP/Block or SoC level.
• Experience in code RTL code Lint, Elaborate and CDC/RDC verification.
• Scripting for tasks automation with Shells (e.g. Bash), TCL, Python or any other language.
• Excellent interpersonal skills, strong initiative and open in engaging and learning various IP sophisticated SoC reference design flow.

“Nice To Have” Skills and Experience :

• Experience in DFT and STA with SDC constraints.
• Experience in Synopsys-VIP usage for Interface IP verification.
• Exposure to physical implementation.

In Return:

We have a friendly and high-performance working environment, where Arm offers a competitive benefits package in France including: private medical insurance (employee and family), 25 days annual leave, 20-day sabbatical every four years, supplementary pension and reduction in working hours.

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