Job title:
Deep Learning Accelerators – Secure Deep Learning Hardware Accelerators Against Fault Injection and Side-Channel Attacks
Company:
Job description
Offer DescriptionCall for expression of interest descriptionThe is a highly prestigious renowned EU-funded scheme. It offers talented scientists a unique chance to set up 2-year research and training projects with the support of a supervising team. Besides providing an attractive grant, it represents a major opportunity to boost the career of promising researchers.Research laboratories in Brittany arethus looking for excellent postdoctoral researchers with an international profile to write a persuasive proposal to apply for a Marie S. Curie Postdoctoral Fellowship grant in 2024 (deadline of the EU call set on 11 September 2024). The topic and research team presented below have been identified in this regard.Main Research Field
- Information Science and Engineering (ENG)
Research sub-field(s)Deep learning accelerators, hardware securityKeywordsDeep learning accelerators, hardware security, fault attacks, countermeasures, fault toleranceResearch project descriptionAre Deep Learning Training Accelerators Secure? Recent studies show how to use side-channels to guess key parameters or inputs from Deep Learning (DL) models running on accelerators. For example, input images of a model were estimated from power traces. However, this project goes further than current practice by studying if private information can be retrieved during the training phase or if it is possible to disrupt the training quality by attacking the accelerators. Our objective is to study training-time hardware attacks and required countermeasures, focusing on fault injections in edge devices and remote side-channel attacks to cloud accelerators.Together with the team members, you will be (1) investigating the vulnerabilities to local and remote Fault Injection (FI) and Side-Channel Analysis (SCA) attacks to custom DL accelerators at the edge and the cloud; and (2) developing adequate countermeasures to mitigate these attacks.For fault-injection, we investigate how FI attacks can impact the integrity and availability of the system (accuracy, training/inference time, energy consumption). For local attacks, we focus on electromagnetic FI and for remote attacks, on clock/power glitches and power distribution attacks (exploiting DVFS mechanisms or through the shared power distribution network of the device).For side-channel analysis, the objective is to understand how SCA attacks can impact the confidentiality of the system by revealing key secret informationlike training/inference inputs and by enabling reverse engineering of DL models and architectures. For local attacks, we focus on capturing power/EM side- channel leakage traces, and for remote attacks on custom sensors deployed in the FPGA fabric or by abusing DVFS mechanisms or further leakage sources to be investigated.The assignment to either SCA or FI topics will be done in accordance with the preferences and backgrounds of the candidates.Supervisor(s)The Postdoctoral Fellow will be supervised by Olivier Sentieys, Professor at University of Rennes holding the Inria Research Chair on Energy-Efficient Computing Systems. He is leading the TARAN team (see description below). His research interests are in the area of computer architectures, computer arithmetic, embedded systems and signal processing, with a focus on system-level design, energy-efficient hardware accelerators (especially for machine learning and data mining), approximate computing (reduced-precision arithmetic, numerical accuracy analysis), and fault tolerance. He previously also worked on power management of energy harvesting sensor networks, signal processing for communications systems and low power wireless (body) sensor networks. He authored or co-authored more than 300 journal or conference papers, hold 6 patents, and served in the technical committees of several international IEEE/ACM/IFIP conferences, including DATE, ICCAD, FPL. He is currently serving in the DATE Executive Committee.Department/ResearchInria is the French national research institute for digital science and technology. World-class research, technological innovation and entrepreneurial risk are its DNA. In 215 project teams, most of which are shared with major research universities, more than 3,900 researchers and engineers explore new paths, often in an interdisciplinary manner and in collaboration with industrial partners to meet ambitious challenges. As a technological institute, Inria supports the diversity of innovation pathways: from open source software publishing to the creation of technological startups (Deeptech).The Inria Centre at Rennes University was established in 1980. The centre has 30 research teams, 24 being shared with the IRISA mixed research unit. Its activities occupy over 600 people, scientists and research innovation support staff, including 50 different nationalities. The Inria Centre at Rennes University covers a wide range of expertise in Computer Science, with scientific priorities such as secure digital society, human-robot-virtual world interactions, digital biology and health and digital ecologyTARAN has recognized experience in computing architectures and design tools for domain-specific hardware architectures. TARAN explores efficient hardware accelerator architectures for DNN inference and training on resource-constrained embedded systems (e.g., on-board satellite, IoT devices) and in accelerated clouds using FPGA and ASIC technologies. TARAN has also expertise in analytical and simulation-based methods for evaluating the accuracy of reduced-precision computation and the reliability of hardware designs.LocationInria Centre at Rennes University, Campus de Beaulieu, Rennes, FranceRequirementsResearch Field Computer science Education Level PhD or equivalentSkills/QualificationsPhD degree in Computer/Electrical Engineering, Computer Science, Embedded Systems, Electronics/Microelectronics. You have a strong background in one/various of the following topics:
- Hardware security (preferably on physical SCA and/or FI attacks)
- Design for FPGAs (HDL or HLS) and associated tools (preferably Xilinx Vivado/Vitis/SDK)
- DNN/CNN accelerators architectures
- Hands-on experience in prototyping and implementations using FPGAs
Other interesting skills you should have that can certainly help are:
- Programming in C/C++/Python
- Use of Linux/Git as development environment
- Microelectronics/VLSI Design
- Good use of laboratory instruments (oscilloscopes, power supplies, etc.)
You are able to speak, write and read English with a very good level (french language is not required).PostDoc candidates should have relevant publications in some of the domains involved (FPGA/HW accelera- tors, architectures for AI, hardware security).Languages ENGLISH Level ExcellentResearch Field Computer scienceAdditional InformationEligibility criteriaAcademic qualification: By 11 September 2024, applicants must bein possession of a doctoral degree, defined as a successfully defended doctoral thesis, even if the doctoral degree has yet to be awarded.Research experience: Applicants must have a maximum of 8 years full-time equivalent experience in research, measured from the date applicants were in possession of a doctoral degree. Years of experience outside research and career breaks (e.g. due to parental leave), will not be taken into account.Nationality & Mobility rules:Applicants can be of any nationality but must not have resided more than 12 months in France in the 36 months immediately prior to the MSCA-PF call deadline on 11 September 2024.Selection processWe encourage all motivated and eligible postdoctoral researchers to send their expressions of interest through the EU Survey application form ( ), before 5th of May 2024. Your application shall include:
- a CV specifying: (i) the exact dates for each position and its location (country) and (ii) a list of publications;
- a cover letter including a research outline (up to 2 pages) identifying the research synergies with the project supervisor(s) and proposed research topics described above.
Estimated timetableDeadline for sending an expression of interest5th May 2024Selection of the most promising application(s)May – June 2024Writing the MSCA-PF proposal with the support of the above-mentioned supervisor(s)June – September 2024MSCA-PF 2024 call deadline11th September 2024Publication of the MSCA-PF evaluation resultsFebruary 2025Start of the MSCA-PF project (if funded)May 2025 (at the earliest)Website for additional job detailsWork Location(s)Number of offers available 1 Company/Institute Centre Inria de l’Université de Rennes Country France City Rennes Postal Code 35000 Street 263, avenue du Général Leclerc GeofieldWhere to apply WebsiteContact State/ProvinceFRANCE CityRennes WebsiteStreet263 avenue du Général Leclerc Postal Code35000 E-Mail[email protected]STATUS: EXPIRED
Expected salary
Location
Rennes, Ille-et-Vilaine
Job date
Sat, 30 Mar 2024 23:51:34 GMT
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