Design Enginner

We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.  

Overview:
As a System & Design Engineer focusing on digital and DSP design of wireless PHY and MAC layer IPs and systems for low-power System-on-Chip IoT products, you will join a specialized team of IP/SoC engineers driving multiple wireless communications technologies such as Bluetooth Low-Energy, 802.15.4 Zigbee/Thread, 802.11 Wi-Fi and proprietary short-range wireless. 

You will be part of a highly-skilled and tight-knit team where everyone can have significant impact on, and responsibility for, the end product. The Rennes site is cross functional and therefore you’ll be interacting firsthand with software designers and customer support team. We strive to strike a good work/life balance and make our environment welcoming and fun, so we seek someone whose technical skills are matched by their interpersonal skills.

Learn more about our IoT products here.

Silicon Labs has a track record of multiple industry firsts and of transforming and disrupting large and diversified markets. Our Design Engineers are at the forefront of that success! 

What You’ll Do:

·       You will take designs through the complete development lifecycle from concept/study to silicon bring-up

·       Research and develop new communication DSP algorithms 

·       Develop innovative new algorithms for patenting or protecting as trade secret

·       Perform architectural studies to determine optimal hardware implementations of PHY and MAC layer designs to meet product requirements

·       Develop and review detailed and concise architecture and design specification documents

·       RTL logic design of modules using Verilog HDL. Designs may include protocol/MAC accelerators, FIR/CIC filters, signal acquisition, timing recovery, mixers, equalizers, FFTs, demodulators, FEC encoders/decoders and AGC

·       Develop low level C-code Firmware for embedded processors

What skills you need:

·       Master level degree in Electrical Engineering, Signal Processing

·       0-3 years of professional experience in digital design with specific focus on DSP and communications. 

·       Experience using Matlab or other high-level modeling language/tool for designing and evaluating communication systems and algorithms

·       Experience in implementing and analyzing fixed-point DSP and numerical processing elements

·       Strong analytical skills based on fundamentals

·       Verilog RTL design with emphasis on DSP/math-centric designs

·       Knowledge of RF transceiver functions and impairments

·       Experience in block and chip-level verification and emulation

·       Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools

·       Knowledge of scripting/language (perl, shell, tcl, python)

·       Excellent written and verbal communications skills (Fluent English)

What we offer:

We offer you a key role in the IoT industry in a dynamic, fast growing and profitable company. Our modern office space close to the brand-new metro line B brings vibrant Rennes city center to our door.   https://www.rennes-business.com/en/why-rennes/
You will also get to work with a fun and great team of top industry experts. At Silicon Labs we also care greatly about our employees and want to be a truly great place to work.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.