PhD Topic: AI for Electronic Design Automation

30 Jan 2024
Job Information

Organisation/Company

Télécom Paris

Research Field

Computer science » Computer architecture

Researcher Profile

First Stage Researcher (R1)

Country

France

Application Deadline

30 Apr 2024 – 00:00 (UTC)

Type of Contract

To be defined

Job Status

Negotiable

Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme

Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

AI for Electronic Design Automation

Modern Day SoCs (System-on-Chips) are extremely complex systems comprising of billions
of transistors, thousands of IP (Hardware Intellectual Property) blocks coming from multiple vendors
all across the globe. These systems have to be optimized for physical constraints, firstly for performance
and power, and also for increasingly difficult fabrication constraints at the current 5nm technology node.
For example the latest A16 Bionic SoC from Apple comprises of over 16 billion transistors at 5nm node,
with maximum frequency upto 3.46 GHz, comprising of multiple core CPU, GPU, NPU and hundreds
of other cores for intra and extra chip communication.

Managing this level of complexity, is simply
beyond the human mind, and use of automated
methods, and traditional machine learning techniques
have been adopted very early in the SoC Design
community. This automated design is a billion dollar
industry in itself called the EDA (Electronic Design
Automation) Industry. A schematic outline of major
design steps are illustrated in Figure 1. Each design
step is again a collection of NP-Complete problems.
[1]. For example a simple chip floorplannig problem
has ~109000 possible states, compared to a game of Go
(~10360) and a game of Chess (~10123). Consequently,
the use of deterministic algorithm will result in a nearinfinite runtime. For this reason the use of Heuristics
(with human intuition)[1] and machine learning
techniques are very common in the EDA field.

![Image] (https://perso.telecom-paristech.fr/chaudhur/eda.png )

Objectives and Methods:

As stated previously, the EDA algorithms are
a collection of NP-Hard Problems which are currently
solved with heuristics-based optimization methods.
The major difference between these algorithms and expert human designers is the absence of reuse of
previous information, knowledge and know-how. These algorithms start from a clean state and try to find the optimum solution, leading to very long runtimes, whereas human experts can usually quickly
find a reasonably good solution, although often sub-optimal.

The backend design tasks such as Chip Placement/Floorplanning is mainly addressed through
GNNs, CNNs [6,7,8,9,10,11,12]. The detailed routing prediction tasks using deep learning techniques
are addressed in [16,17] and congestion prediction in [13,14]. Ref. [15] tries to solve the Clock Tree
Synthesis with GANs. The Backend verifications tasks are addressed in refs. [30,31].

The main goal of this PhD. Thesis is AI –Driven Floorplanning, Placement/Routing of VLSI
circuits. We plan to use existing deep learning based method for floorplanning, and use a Graph Neural
Network (GNN) based approach for one-shot routing of connections. This is again a very ambitious
goal which has not been addressed before. The approaches in literature use an iterative and time
consuming process. We will on the other hand, generate a large dataset of good quality routing using
existing tools, and training our networks to predict routes instantaneously.
Here is brief plan for 3 years of PhD. (subject to change depending on the orientation of the student)

References

[1] A graph placement methodology for fast chip design. Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim
Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang,
Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter & Jeff Dean, 2021. Nature, 594(7862), pp.207-212

[2] CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA), Zhuomin Chai,
Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, and Ru Huang, SCIENCE CHINA Information Sciences 2022

[6] SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution
Improvement Ismail Bustany,Andrew B. Kahng,Ioannis Koutis, Bodhisatta Pramanik, and Zhiang Wang DAC 2022

[7] LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling Liangjian Wen, Yi Zhu, Lei Ye,
Guojin Chen, Bei Yu, Jianzhuang Liu, and Chunjing Xu ICCAD 2022

[8] Floorplanning with Graph Attention Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and
Li Shang DAC 2022

[9] GraphPlanner: Floorplanning with Graph Neural Network Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang,
Fan Yang, Xuan Zeng, and Li Shang TODAES 2022

[10] TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs, Yi-Chen Lu, Sai Surya Kiran Pentapati,
Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim, DAC 2020

[11] DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning, Yi-Chen Lu,
Haoxing Ren, Hao-Hsiang Hsiao, and Sung Kyu Lim, ISPD 2023

[12] MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning Yao Lai, Yao Mu, and Ping Luo, NeurIPS 2022

[13] LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction, Bowen Wang, Guibao Shen, Dong Li, Jianye Hao,
Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, and Pheng Ann Heng, DAC 2022

[14] Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net, Kyeonghyeon Baek,
Hyunbum Park, Suwan Kim, Kyumyung Choi, and Taewhan Kim, ICCAD 2022

[15] A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning, Yi-Chen Lu, Jeehyun Lee,
Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim, TCAD 2022

[16] On Joint Learning for Solving Placement and Routing in Chip Design, Ruoyu Cheng and Junchi Yan, NeurIPS 2021

[17] Reinforcement Learning Guided Detailed Routing for FinFET Custom Circuits, Hao Chen, Kai-Chieh Hsu, Walker J. Turner, PoHsuan Wei, Keren Zhu, David Z. Pan, and Haoxing Ren, ISPD 2023

[30] Hotspot Detection via Attention-Based Deep Layout Metric Learning, Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, and
Bei Yu, TCAD 2022.

[31] Efficient Hotspot Detection via Graph Neural Network, Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, and Xuan Zeng, DATE 2022.

Requirements
Additional Information

Website for additional job details

https://www.hipeac.net/jobs/14519/phd-topic-ai-for-electronic-design-automation/

Work Location(s)

Number of offers available

1

Company/Institute

Télécom Paris

Country

France

City

Paris

Geofield

Where to apply

E-mail

[email protected]

Contact

City

Paris

Website

https://www.youtube.com/user/TelecomParisTech1
https://www.telecom-paris.fr/
https://twitter.com/TelecomPTech
https://www.linkedin.com/school/telecom-paris/

STATUS: EXPIRED