Allegro MicroSystems
Job title:
Senior Digital Design Engineer
Company:
Allegro MicroSystems
Job description
The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future. With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.As part of our innovation, we recognize that our team members are unique and that our work locations must be adaptable. At Allegro we flex. Flex@Allegro is our approach to hybrid work that empowers managers and their team members to decide where and when work will be done. Ask what Flex@Allegro can mean for you.In this position, you will be part of a growing and dynamic team that primarily focuses on developing power management and high voltage applications IC products.You will have the opportunity to work with industry leading customers to develop advanced solutions for Automotive, Industrial, Communications and Computer systems.ResponsibilitiesInterpreting requirements specificationTaking part in the specification phase of ICBlock and top-level digital design from specification to synthesized and STA clean netlistInterface with physical implementation team for the definition of physical, timing and DFT constraintsInterface with product development team to develop test strategyEssential QualificationsProspective candidates should have a PhD or Master degree (or equivalent) in Electronics or a related field and a solid experience in mixed signal IC design. The candidate should be proficient in developing block and top-level timing constraints for STA and P&R handoff.+4 years experience in a similar role.Familiarity with serial interfaces such as SPI, I2C, UART, Manchester, CAN, etc.Familiarity with Cadence toolsets, Matlab, Simulink modeling.Experience in developing verification environments in SV/UVM and using SVA.Knowledge of Tcl and Python or similar.Familiarity with Alter FPGAsCompetent in digital design and DFT techniquesKnowledge of front-end RTL design using Verilog or VHDLExperience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog/System VerilogGood verbal and written communication skillsAbility to work in a multi-cultural team environment
Expected salary
Location
Milano
Job date
Sat, 15 Mar 2025 05:43:44 GMT
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